To achieve high rectification efficiency at full-load, multiple power transistors are connected in parallel in a single synchronous rectifier (SR) location to effectively reduce the SR resistance by a factor of the number of transistor in parallel. For example, three transistors in parallel have an equivalent on resistance equal to ⅓rd of a single device. However, the trade-off associated with paralleling multiple devices is a penalty in light-load efficiency as the gate loss increases by a factor of the number of devices in parallel. In the previous example, three devices in parallel have three times the gate loss of a single device. At light load (low power), gate loss dominates, and at full-load (high power) conduction loss dominates, so a trade-off inevitably exists. In the case of power converters having a center-tap secondary winding, the voltage stress is greater than the reflected input voltage. Therefore, the SRs require higher voltage rating with higher gate charge than lower voltage devices with equivalent on-resistances.
Realistically, the higher voltage parts have higher gate charge and higher on-resistance, exacerbating the need for parallel devices and increasing the light-load efficiency penalty. Using parallel transistors in place of a single device is common practice to increase the current handling capability of a power converter. However, the devices are typically symmetric and driven by the same signal. One approach uses FET modulation, where the sizes of FETs and gate drive voltage are modulated according to load so as to improve efficiency across the load range for non-isolated DC/DC converters. At light load, a small FET is used with low gate drive to reduce capacitive-related losses that dominate at that load range. As the load increases, the FET size increases along with gate drive voltage to minimize conduction losses which form the dominant loss mechanism at mid-high current. This concept was extended to isolated topologies where symmetric synchronous rectifiers were used in parallel. As the load reduces, the parallel synchronous rectifiers are turned off, and the gate drive voltage applied to the remaining SRs is reduced. There are a couple of disadvantages to this approach. First, gate voltage adjustment usually provides power savings for the converter, but not the system. The losses incurred by the gate voltage supply typically equal the savings experienced by the power converter. So in real systems, it is not worth the effort. Second, the use of symmetric FETs limits the achievable light-load efficiency as the SRs are typically large die (chips).
Existing solutions adjust the conduction time of the synchronous rectifiers depending on load. In one case, synchronous rectifiers conduct during both the energy transfer and freewheeling intervals of the switching cycle at high load conditions where energy transfer current is the current associated with one or more primary-side devices connecting the input voltage to the transformer primary so as to transfer energy from the source to the load. Freewheeling current is the current pulled through the synchronous rectifiers by the filter inductor while all primary-side devices are off. As the load reduces, the synchronous rectifiers only conduct the energy transfer current while the body diodes conduct the freewheeling current. At even lighter load, the synchronous rectifiers remain off and the body diodes conduct all current. There are two energy transfer intervals per cycle (positive and negative), and their sum represents the duty cycle according to
  D  =                    t                  on          +                    +              t                  on          -                            T      sw      where ton is the on-time of the appropriate primary-side devices to create the voltage incident VAB on the transformer primary for the positive and negative half cycles indicated by the + and − symbols, respectively, and Tsw is the switching period. The freewheeling intervals occur when VAB is zero yet the current in the SRs is non-zero. The sum of freewheeling time per switching period represents 1-D. If parallel devices are used with the second conventional solution described above, the converter will have worse light-load performance than the first conventional solution described above because the second solution cannot turn individual devices off.